1. Field of the Invention
The present invention relates to a charge and discharge control circuit and a battery device for detecting reverse connection of a charger, and more particularly, to a charge and discharge control circuit and a battery device for preventing a breakage of the charge and discharge control circuit and the battery device when a charger is reversely connected.
2. Description of the Related Art
At present, various kinds of portable electronic devices have become widespread. The portable electronic devices are generally driven by a battery device equipped with a battery. FIG. 4 illustrates a circuit diagram of a charge and discharge control circuit and a battery device according to the related art. The charge and discharge control circuit and the battery device according to the related art include an overcharge detection circuit 411, an overdischarge detection circuit 412, an overcurrent detection circuit 413, a delay circuit 415, a logic circuit 417, a charger reverse connection detection circuit 106, a VDD terminal 111, a VSS terminal 112, a DO terminal 113, a CO terminal 114, a VM terminal 115, external terminals 120 and 121, a secondary battery 101, a charge control N-channel FET transistor 108, a discharge control N-channel FET transistor 107, and a resistor 104.
In a charger reverse connection state in which a positive terminal of a charger is connected to the external terminal 121 and a negative terminal of the charger is connected to the external terminal 120, voltages of the VM terminal 115 and the external terminal 121 become closer to a power supply voltage as a voltage of the secondary battery 101, although being closer to a ground voltage in the normal state. When the voltage of the VM terminal 115 becomes a predetermined voltage, the charger reverse connection detection circuit 106 detects the reverse connection of the charger and outputs a signal to the logic circuit 417. The logic circuit 417 outputs signals of High and Low to gates of the charge control N-channel FET transistor 108 and the discharge control N-channel FET transistor 107, respectively. In this case, there exists no delay period from the detection of the reverse connection of the charger and the output of the High and Low signals. The charge control N-channel FET transistor 108 is turned on to supply a current, and the discharge control N-channel FET transistor 107 is turned off to supply only a charge current due to a parasitic diode. Then, the charger reverse connection detection circuit 106 stops the discharge of the secondary battery 101.
In this manner, when entering the charger reverse connection state, the discharge of the secondary battery 101 is stopped (see, for example, Japanese Patent Application Laid-open No. 2009-247100).
In the charge and discharge control circuit and the battery device according to the related art, however, there is a problem in that, after the reverse connection of the charger is detected to stop the discharge of the secondary battery, a current may flow from the VM terminal 115 to the VDD terminal 111 via a parasitic diode.
When the reverse connection of the charger is detected to stop the discharge, the voltage of the VM terminal 115 becomes a value determined by adding a voltage of the charger to the voltage of the secondary battery, and hence the voltage of the VM terminal 115 becomes higher than the voltage of the VDD terminal 111. Then, due to the parasitic diode connected from the VM terminal 115 to the VDD terminal 111, a current flows from the VM terminal 115 toward the VDD terminal 111. This current flows from the VM terminal 115 to the VDD terminal 111 and the external terminal 120. When this current is represented by Ivm, the voltage of the secondary battery is represented by Vbat, a resistance value between the VDD terminal 111 and the external terminal 120 is represented by R1, and a withstand voltage between the VDD terminal 111 and the VSS terminal 112 of the charge and discharge control circuit is represented by Vmax, a voltage of Vbat+Ivm×R1 is applied between the VDD terminal 111 and the VSS terminal 112 of the charge and discharge control circuit.
In this case, when (Vbat+Ivm×R1)>Vmax is established, a voltage higher than the withstand voltage is applied to the charge and discharge control circuit.